High-capacity nonvolatile memory is under active development. This type of memory is capable of low voltage/low current operation, high-speed switching, and memory cell downscaling/high integration.
A high-capacity memory array has a large number of metal wiring lines, called bit lines and word lines, arranged therein. To write to a single memory cell, voltage is applied to a bit line and a word line connected to the cell. Memory devices in which memory cells are arranged three-dimensionally have been proposed using a stacked body in which insulating layers and conductive layers serving as word lines are alternatingly stacked.
Further, by, for example, providing an insulator that passes through the memory cells and the word lines to separate the memory cells and the word lines, the capacity of the memory array can be increased. However, in the cases where such an insulator is provided, parasitic transistors are formed by adjacent pluralities of word lines and the insulator. Thus, when writing to a memory cell is performed, the respective parasitic transistor is switched ON, current flows between adjacent word lines, and insufficient current flows to the memory cell.
Consequently, there has been an issue that memory cell current does not increase, and a threshold voltage of the memory cell does not increase.